Hardware Implementation of Algorithms

Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine

Information Systems / Genetic Algorithms / Field-Programmable Gate Arrays / Genetic Algorithm / System Architecture / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route

A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine

Information Systems / Genetic Algorithms / Field-Programmable Gate Arrays / Genetic Algorithm / System Architecture / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route / Hardware / Global Optimization / Software Implementation / Search Engine / Population Size / Field Programmable Gate Array / Real Time / Robustness / Real Time Application / Evolvable Hardware / Fitness Function / Experimental Tests / Hardware Implementation of Algorithms / Random Number Generation / Evolutionary / RANDOM NUMBER GENERATOR / Electrical And Electronic Engineering / Mutation Rate / Place and Route

EFFICIENT SIGNAL PROCESSING USING SYNTACTIC PATTERN RECOGNITION METHODS

Signal Processing / Hardware Design / Signal and Image Processing / Syntactic Pattern Recognition / Field Programmable Gate Array / Real Time / Data representation / Electrocardiogram / Natural language interface / Source Code / Hardware Implementation of Algorithms / Real Time / Data representation / Electrocardiogram / Natural language interface / Source Code / Hardware Implementation of Algorithms

EFFICIENT SIGNAL PROCESSING USING SYNTACTIC PATTERN RECOGNITION METHODS

Signal Processing / Hardware Design / Signal and Image Processing / Syntactic Pattern Recognition / Field Programmable Gate Array / Real Time / Data representation / Electrocardiogram / Natural language interface / Source Code / Hardware Implementation of Algorithms / Real Time / Data representation / Electrocardiogram / Natural language interface / Source Code / Hardware Implementation of Algorithms

An Efficient On-Board Lossless Compression Design for Remote Sensing Image Data

Remote Sensing / Geoscience and remote sensing / Earth Observation / Radiometric Calibration / Lossless Image Compression / Space Application / Hardware Implementation of Algorithms / System performance / Multispectral Images / Remote Sensing Image / Lossless data compression / Error Resilience / Lossless Compression / Space Application / Hardware Implementation of Algorithms / System performance / Multispectral Images / Remote Sensing Image / Lossless data compression / Error Resilience / Lossless Compression

Codesign of Fully Parallel Neural Network for a Classification Problem

Image Processing / Neural Network / Cost Reduction / Hardware Implementation of Algorithms / Signal - to - noise ratio

An efficient hardware design for intra-prediction in H.264/AVC decoder

Video Compression / Image coding / Hardware Design / Algorithm Design / Digital Video / Very high throughput / Hardware Implementation of Algorithms / Intra Prediction / Very high throughput / Hardware Implementation of Algorithms / Intra Prediction

A general-purpose dynamically reconfigurable SVM

Fixed Point Theory / Support vector machine / Partial Reconfiguration / Hardware Implementation of Algorithms / Dynamic Reconfiguration / Sequential Minimal Optimization (SMO)

Video compression and VLSI

Algorithms / Speech Synthesis / Multimedia / VLSI / Video Compression / Videoconference / Very Large Scale Integration / Hardware / Chip / Hardware Implementation of Algorithms / Application Software / Videoconference / Very Large Scale Integration / Hardware / Chip / Hardware Implementation of Algorithms / Application Software

Customizable elliptic curve cryptosystems

Distributed Computing / Computer Hardware / Cryptography / Field-Programmable Gate Arrays / Hardware Design / Software Implementation / Field Programmable Gate Array / Public key cryptography / Galois Fields / Hardware Implementation of Algorithms / Elliptic Curve Cryptography / Finite Field / Electrical And Electronic Engineering / Parallel Architecture / Elliptic curve cryptosystem / Parametric Model / Software Implementation / Field Programmable Gate Array / Public key cryptography / Galois Fields / Hardware Implementation of Algorithms / Elliptic Curve Cryptography / Finite Field / Electrical And Electronic Engineering / Parallel Architecture / Elliptic curve cryptosystem / Parametric Model

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